Job Description
Doing Logical Synthesis, understanding of digital P&R, Formal Verification.
Knowledge of Synopsys sign-off tools.
Analyze and verify to make sure design meet all requirements of functionality, performance, area and reliability.
Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures
Defining Clock / Reset domain crossing design constraints and evaluating violations using CDC / RDC tools
Analyze timing arc and liberty quality from analog IPs.
Analyze timing violation and suggestion fixes.
Analyze, summarize and generate status updates from synthesis and timing report.
Complete all design quality checks and data quality checks
Locate in Da Nang
Skills Requirements
BS / MS / PhD in Electronics Engineering, Electromechanics, Telecommunications.
4+ years of experience in RTL-to-GDS design
Deep technical knowledge of RTL-to-GDS full design flow
Strong scripting skills (Perl, tcl, Python)
Good English communication both verbally and in writing
Demonstrate good analysis and problem-solving skills
Highly responsible, result oriented.
Self-motivated and highly enthusiasm in technology and solving problems
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
