Do TOP simulation for big macro of a High Bandwidth Interface design including Power Integrity, Signal integrity, Timing budget calculation, Co-simulation and EMIR,
Analyze and verify to ensure the design to meet all requirements of performance and reliability.
Work closely with IP design teams to ensure the quality of layout for power, signals.
Design analysis and solve problems of noise, margin, signal integrity, power integrity.
Complete all check lists of the design quality and data quality.
Do design reviews across global team
Company digital / system engineers to integrate analog designs into mixed signal system. Perform mixed signal verification combining both analog and digital blocks.
Work closely with Test Lab to debug silicon issues related to Power / Noise / Top chip timing.
Training fresh engineers and interns
BS / MS in Electronics Engineering, Electromechanics, Telecommunications.
4+ years of experience in Analog, Mixed Signal, Memory or Custom logic Circuit design.
Solid knowledge of CMOS Analog design knowledge and techniques
Solid skill with circuit design tools : SNSP Custom Designer, Cadence Virtuoso
Solid understanding circuit simulation tools : Hspice or Spectre or Custom Sim
Good understanding of layout effects on circuit performance.
Experienced with writing design review presentations and circuit verification reports
Good English communication both verbally and in writing
Strong analytic skills
Great team player, willing to support others.
Highly responsible, result oriented.
Self-motivated and highly enthusiasm in technology and solving problems
Leadership skill and experience is a plus
Familiar with high speed analog designs, IO designs, PLL / DLL is a plus
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.