Work in a Digital and Verification Development team during the development and validation of complex digital mix signals for high-speed interface IP.
Test planning, checklist, Coverage and Assertion planning
Hands on experience in creating detailed Verification Environment from Functional Specifications
Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
Writing test cases, checkers, and coverage that implement the verification test plan.
Debug of simulations, including those of real signals modeled using SV for analog
RTL, GLS & Co-simulations & coverage closure
Participate in technical reviews and contribute actively
Participate in customer support with bring-up of IP in customer simulation environment
Follow and improve development process ensuring high quality output.
BS / MS / PhD in Electronics Engineering, Electromechanics, Telecommunications.
5+ years of experience in Design Logic Verification
Strong skill with VCS / Verdi simulation tools, Formal verification tool (vc formal)
Knowledge of UPF, UVM(Universal Verification Methodology) and SVA (System-Verilog Assertion) is a plus
Strong debug skills and demonstrated experiences in Perl / TCL / Python scripting is a plus
Highly responsible, result oriented
Good English communication both verbally and in writing
Great team player, willing to support others
Self-motivated and highly enthusiasm in technology and solving problems
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.