and Requirements
ASIC Physical Design Engineer, Sr II
Description :
In this role, you will be responsible for :
Physical Implementation of high speed interface IPs across multiple process technologies.
Driving all aspects from RTL to GDS including timing and physical sign-off.
Close interaction and collaborative team work with multiple functional groups (front end, analog, CAD) and the product team.
Requirements :
8 + years of physical design experience with recent contribution to project tape-outs
Strong understanding of the full design cycle from RTL to GDSII
Experience with advanced FinFET nodes including low-power design techniques.
A solid engineering understanding of the underlying concepts of IC design, implementation flows, physical and timing signoff and methodologies for deep submicron design.
Methodology driven with strong software and scripting skills (Perl, Tcl, Python); knowledge of CAD automation methods.
Proficient with place and route, synthesis, timing and power analysis tools ICC2, Design Compiler, PrimeTime, Redhawk.
Proficient with physical verification tools and flows ICV and other PV tools for LVS, DRC, ERC, PERC.
Excellent communication skills, ability to think and communicate at different levels of abstraction.
Demonstrates master skill at analysis and problem-solving.
Accountability, self-motivation, positive attitude and teamwork.
Has a strong desire to learn and explore new technologies.
Education Requirements :
BSEE and 8+ years; MSEE and 6 year +
