Responsible for specification development, architecture design and RTL development for High Bandwidth Interface PHY IP and Test chip.
Define synthesis design constraints, resolve issues related to STA and Gate level simulation.
Collaborate with Verification team and review the Verification plan mapping with specification.
Collaborate with Controller and maybe Zebu team for sub system design and verifications.
Familiar with RTL to GDS flow to follow up with other teams during the logic implementation phases.
Collaborate with Lab team to debug silicon issues related to logic design.
Perform Project leadership role if required.
May work directly with customer to resolve technical issues related to RTL.
Contribute to the digital flow development.
Train junior RTL engineers.
BS / MS / PhD in Electronics Engineering, Telecommunications.
5+ years of experience in RTL design for ASIC or PHY IP.
Familiar with tool VCS, Verdi, Spyglass or similar tools
Solid knowledge on clock domain crossing
Strong scripting skills (Perl, tcl, Python)
Familiar with APB, JTAG
Strong communication both verbally and in writing
Experience in Analog Mixed Signal IP is a big plus
Good English in both speaking and writing.
Highly responsible, result oriented.
Self-motivated and highly enthusiasm in technology and solving problems
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.