Should be strong in technical concepts, fundamentals, and good team player. The role involves daily technical interaction with local, US counter parts.
He / She will be part of SNPS DDR, HBI IP implementation team and responsible for the implementation and integration of world class Die-to-Die IPs at the cutting-edge technology nodes (14nm,10nm,7nm and below).
Timing closure above 2GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job.
Prior working knowledge in the DDR / HBM / HBI timing closure, implementation would be an added advantage.
He / She should be able to help other junior engineers within the team.
This role is for a technical ladder and so it requires hands-on working knowledge preferably with SNPS tools like DC, PT, PT-SI and ICC2.
Typically requires 5-8 years of experience after graduation from a reputed university.
Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world’s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors.
All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications.
And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence.
The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.
If you share our passion for innovation, we want to meet you.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.