Job Description
Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees...
Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
Understand and apply Analog Layout techniques to ensure design meet performance with minimum area and good yield.
Participate in building and enhancing layout flow for faster, higher quality design process.
Do layout verification for DRC / LVS / ERC / ANT / ESD / DFM
Do PERC verification for ESD / LUP checks
Complete all design quality checks and data quality checks
Work with Place and Route engineer to integrate analog layouts into top level.
Do design reviews across global team
May collaborate in package design (interposer design, RDL design)
Work closely with design team in Viet Nam, USA and Italy to ensure the success of the whole product.
May join research programs to implement new ideas for future products and flows
May lead a layout team to complete a full design block
May mentor junior layout engineers or interns
Skills Requirements :
BS in Electronics Engineering, Electromechanics, Telecommunications.
4+ years of experience in custom layout.
Familiar with Layout entry tools : Cadence, Synopsys
Familiar with Layout verification tools : Mentor Calibre, Synopsys ICV
Understand basic semiconductor fabrication processes
Understand MOSFET fundamentals
Understand layout techniques for high speed, matching, ESD, Latchup, Antenna, EMIR.
Experienced with writing layout review presentations and layout verification reports
Good English communication
Good team player
Self-motivated
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
